Micro-optimizations at the RavenDB vNext storage engine are critical to achieve 50K+ write requests per second on single node commodity hardware. In this talk we'll explore the use of the new hardware intrinsic introduced on CoreCLR 2.1 in the context of real-life critical path bottlenecks. We will touch on hardcore topics like CPU architecture and its effect on instruction latency and throughput, the effect of cache behaviors (hit/miss ratio, poisoning), prefetching, etc. The talk is aimed at engineers doing micro-optimization and high performance computing.
Federico is a cofounder of Corvalius, a R&D company, and of Codealike, a Developer Analytics company. He has been working on algorithmic performance for the last 10 years, both with CPU and specialized hardware like GPUs. His experience ranges from banking software performance tuning to database engine optimization. He enjoys reading in binary and tinkering with registers and caches. Among his technology interests are highly distributed systems, massively parallel technology, low-level optimization and high-performance computer graphics.